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?2015 integrated device technology, inc. august 2015 dsc 5628/10 1 ? functional block diagram features: 512k x 18 synchronous bank-switchable dual-ported sram architecture ? 64 independent 8k x 18 banks ? 9 megabits of memory on chip bank access controlled via bank address pins high-speed data access ? commercial: 3.4ns (200mhz)/3.6ns (166mhz)/ 4.2ns (133mhz) (max.) ? industrial: 3.6ns (166mhz)/4.2ns (133mhz) (max.) selectable pipelined or flow-through output mode counter enable and repeat features dual chip enables allow for depth expansion without additional logic full synchronous operation on both ports ? 5ns cycle time, 200mhz operation (14gbps bandwidth) ? fast 3.4ns clock to data out ? 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200mhz ? data input, address, byte enable and control registers ? self-timed write allows fast cycle time separate byte controls for multiplexed bus and bus match- ing compatibility lvttl- compatible, 3.3v (150mv) power supply for core lvttl compatible, selectable 3.3v (150mv) or 2.5v (100mv) power supply for i/os and control signals on each port industrial temperature range (-40c to +85c) is available at 166mhz and 133mhz available in 208-pin fine pitch ball grid array (fpbga) and 256-pin ball grid array (bga) supports jtag features compliant with ieee 1149.1 green parts available, see ordering information high-speed 3.3v 512k x 18 synchronous bank-switchable dual-port static ram with 3.3v or 2.5v interface IDT70V7339S 8kx18 memory array (bank 63) mux mux pl/ ft l opt l clk l ads l cnten l repeat l r/ w l ce 0l ce 1l ub l lb l oe l i/o 0l-17l a 12l a 0l jtag 8kx18 memory array (bank 1) mux mux 8kx18 memory array (bank 0) mux mux control logic i/o control bank decode address decode i/o 0r-17r a 12r a 0r control logic i/o control bank decode address decode 5628 drw 01 ba 5r ba 4r ba 3r ba 2r ba 1r ba 0r ba 5l ba 4l ba 3l ba 2l ba 1l ba 0l , pl/ ft r opt r clk r ads r cnten r repeat r r/ w r ce 0r ce 1r ub r lb r oe r tms tck trst tdi tdo note: 1. the bank-switchable dual-port uses a true sram core instead of the traditional dual-port sram core. as a result, it has unique operating characteristics. please refer to the functional description on page 18 for details.
6.42 2 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges description: the idt70v7339 is a high-speed 512kx18 (9mbit) synchronous bank-switchable dual-ported sram organized into 64 independent 8kx18 banks. the device has two independent ports with separate control, address, and i/o pins for each port, allowing each port to access any 8kx18 memory block not already accessed by the other port. accesses by the ports into specific banks are controlled via the bank address pins under the user's direct control. registers on control, data, and address inputs provide minimal setup and hold times. the timing latitude provided by this approach allows systems to be designed with very short cycle times. with an input data pin configuration (1,2,3,4) notes: 1. all v dd pins must be connected to 3.3v power supply. 2. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v ih (3.3v), and 2.5v if opt pin for that port is set to v il (0v). 3. all v ss pins must be connected to ground supply. 4. package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking. a17 v ss b17 nc c17 v ss d17 i/o 7r e16 v ss e17 nc d16 i/o 7l c16 nc b16 i/o 8l a16 nc a15 opt l b15 v ddqr c15 i/o 8r d15 v ddql e15 nc e14 i/o 6l d14 nc d13 v dd c12 a 6l c14 v dd b14 v ss a14 a 0l a12 cnten l b12 a 5l c11 r/ w l d12 a 3l d11 repeat l c10 v ss b11 ads l a11 clk l d8 lb l c8 ub l a9 nc d9 v dd c9 ce 1l b9 ce 0l d10 oe l c7 a 10l b8 nc a8 a 8l b13 a 1l a13 a 4l a10 v dd d7 a 7l b7 a 9l a7 a 12l b6 ba 0l c6 ba 1l d6 a 11l a5 nc b5 ba 4l c5 ba 5l d5 ba 2l a4 tdo b4 tdi c4 pl/ ft l d4 nc a3 v ss b3 nc c3 v ddqr d3 i/o 10l d2 v ss c2 i/o 9r b2 v ss a2 nc a1 io 9l b1 nc c1 v ddql d1 nc e1 i/o 11l e2 nc e3 v ddqr e4 i/o 10r f1 v ddql f2 i/o 11r f3 nc f4 v ss g1 nc g2 v ss g3 i/o 12l g4 nc h1 v dd h2 nc h3 v ddqr h4 i/o 12r j1 v ddql j2 v dd j3 v ss j4 v ss k1 i/o 14r k2 v ss k3 i/o 13r k4 v ss l1 nc l2 i/o 14l l3 v ddqr l4 i/o 13l m1 v ddql m2 nc m3 i/o 15r m4 v ss n1 nc n2 v ss n3 nc n4 i/o 15l p1 i/o 16r p2 i/o 16l p3 v ddqr p4 nc r1 v ss r2 nc r3 i/o 17r r4 tck t1 nc t2 i/o 17l t3 v ddql t4 tms u1 v ss u2 nc u3 pl/ ft r u4 nc p5 trst r5 ba 4r u6 a 11r p12 cnten r p8 a 8r u10 oe r p9 nc r8 nc t8 ub r u9 v dd p10 v dd t11 r/ w r u8 lb r p11 clk r r12 a 5r t12 a 6r u12 a 3r p13 a 4r p7 a 12r r13 a 1r t13 a 2r u13 a 0r r6 ba 0r t5 ba 5r u7 a 7r u14 v dd t14 v ss r14 v ss p14 nc p15 i/o 1l r15 v ddql t15 nc u15 opt r u16 nc u17 i/o 0l t16 v ss t17 nc r17 v ddqr r16 i/o 0r p17 nc p16 v ss n17 i/o 2l n16 nc n15 v ddql n14 i/o 1r m17 v ddqr m16 i/o 2r m15 nc m14 v ss l17 i/o 4l l16 v ss l15 i/o 3l l14 nc k17 v ss k16 i/o 4r k15 v ddql k14 i/o 3r j17 v ddqr j16 v ss j15 v dd j14 v ss h17 i/o 5r h16 v ss h15 nc h14 v dd g17 nc g16 i/o 5l g15 v ddql g14 nc f17 v ddqr f16 nc f14 v ss 70v7339bf bf-208 (5) 208-pin fpbga top view (6) f15 i/o 6r r9 ce 0r r11 ads r t6 ba 1r t9 ce 1r a6 ba 3l b10 v ss c13 a 2l p6 ba 3r r10 v ss r7 a 9r t10 v ss t7 a 10r u5 ba 2r 5628 drw 02c u11 repeat r register, the idt70v7339 has been optimized for applications having unidirectional or bidirectional data flow in bursts. an automatic power down feature, controlled by ce 0 and ce 1 , permits the on-chip circuitry of each port to enter a very low standby power mode. the dual chip enables also facilitate depth expansion. the 70v7339 can support an operating voltage of either 3.3v or 2.5v on one or both ports, controllable by the opt pins. the power supply for the core of the device(v dd ) remains at 3.3v. please refer also to the functional description on page 18.
6.42 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges 3 pin configuration (1,2,3,4) (con't.) notes: 1. all v dd pins must be connected to 3.3v power supply. 2. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v ih (3.3v), and 2.5v if opt pin for that port is set to v il (0v). 3. all v ss pins must be connected to ground supply. 4. package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking. 70v7339bc bc-256 (5) 256-pin bga top view (6) e16 i/o 7r d16 i/o 8r c16 i/o 8l b16 nc a16 nc a15 nc b15 nc c15 nc d15 nc e15 i/o 7l e14 nc d14 nc d13 v dd c12 a 6l c14 opt l b14 v dd a14 a 0l a12 a 5l b12 a 4l c11 ads l d12 v ddqr d11 v ddqr c10 clk l b11 repeat l a11 cnten l d8 v ddqr c8 nc a9 ce 1l d9 v ddql c9 lb l b9 ce 0l d10 v ddql c7 a 7l b8 ub l a8 nc b13 a 1l a13 a 2l a10 oe l d7 v ddqr b7 a 9l a7 a 8l b6 a 12l c6 a 10l d6 v ddql a5 ba1 l b5 ba 2l c5 ba 0l d5 v ddql a4 ba 4l b4 ba 5l c4 ba 3l d4 pl/ ft l a3 nc b3 tdo c3 v ss d3 nc d2 i/o 9r c2 i/o 9l b2 nc a2 tdi a1 nc b1 nc c1 nc d1 nc e1 i/o 10r e2 i/o 10l e3 nc e4 v ddql f1 i/o 11l f2 nc f3 i/o 11r f4 v ddql g1 nc g2 nc g3 i/o 12l g4 v ddqr h1 nc h2 i/o 12r h3 nc h4 v ddqr j1 i/o 13l j2 i/o 14r j3 i/o 13r j4 v ddql k1 nc k2 nc k3 i/o 14l k4 v ddql l1 i/o 15l l2 nc l3 i/o 15r l4 v ddqr m1 i/o 16r m2 i/o 16l m3 nc m4 v ddqr n1 nc n2 i/o 17r n3 nc n4 pl/ ft r p1 nc p2 i/o 17l p3 tms p4 ba 3r r1 nc r2 nc r3 trst r4 ba 5r t1 nc t2 tck t3 nc t4 ba 4r p5 ba 0r r5 ba 2r p12 a 6r p8 nc p9 lb r r8 ub r t8 nc p10 clk r t11 cnten r p11 ads r r12 a 4r t12 a 5r p13 a 3r p7 a 7r r13 a 1r t13 a 2r r6 a 12r t5 ba 1r t14 a 0r r14 opt r p14 nc p15 nc r15 nc t15 nc t16 nc r16 nc p16 i/o 0l n16 nc n15 i/o 0r n14 nc m16 nc m15 i/o 1l m14 i/o 1r l16 i/o 2r l15 nc l14 i/o 2l k16 i/o 3l k15 nc k14 nc j16 i/o 4l j15 i/o 3r j14 i/o 4r h16 i/o 5r h15 nc h14 nc g16 nc g15 nc g14 i/o 5l f16 i/o 6l f14 i/o 6r f15 nc r9 ce 0r r11 repeat r t6 a 11r t9 ce 1r a6 a 11l b10 r/ w l c13 a 3l p6 a 10r r10 r/ w r r7 a 9r t10 oe r t7 a 8r e5 v dd e6 v dd e7 v ss e8 v ss e9 v ss e10 v ss e11 v dd e12 v dd e13 v ddqr f5 v dd f6 v ss f8 v ss f9 v ss f10 v ss f12 v dd f13 v ddqr g5 v ss g6 v ss g7 v ss g8 v ss g9 v ss g10 v ss g11 v ss g12 v ss g13 v ddql h5 v ss h6 v ss h7 v ss h8 v ss h9 v ss h10 v ss h11 v ss h12 v ss h13 v ddql j5 v ss j6 v ss j7 v ss j8 v ss j9 v ss j10 v ss j11 v ss j12 v ss j13 v ddqr k5 v ss k6 v ss k7 v ss k8 v ss l5 v dd l6 v ss l7 v ss l8 v ss m5 v dd m6 v dd m7 v ss m8 v ss n5 v ddqr n6 v ddqr n7 v ddql n8 v ddql k9 v ss k10 v ss k11 v ss k12 v ss l9 v ss l10 v ss l11 v ss l12 v dd m9 v ss m10 v ss m11 v dd m12 v dd n9 v ddqr n10 v ddqr n11 v ddql n12 v ddql k13 v ddqr l13 v ddql m13 v ddql n13 v dd f7 v ss f11 v ss 5628 drw 02d
6.42 4 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges pin names left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables r/ w l r/ w r read/write enable oe l oe r output enable ba 0l - ba 5l ba 0r - ba 5r bank address (4) a 0l - a 12l a 0r - a 12r address i/o 0l - i/o 17l i/o 0r - i/o 17r data input/output clk l clk r clock pl/ ft l pl/ ft r pipeline/flow-through ads l ads r address strobe enable cnten l cnten r counter enable repeat l repeat r counter repeat (3) lb l , ub l lb r , ub r byte enables (9-bit bytes) v ddq l v ddqr power (i/o bus) (3.3v or 2.5v) (1) opt l opt r option for selecting v ddqx (1,2) v dd power (3.3v) (1) v ss ground (0v) tdi test data input tdo test data output tck test logic clock (10mhz) tms te st mod e se le ct trst reset (initialize tap controller) 5628 tbl 01 notes: 1. v dd , opt x , and v ddqx must be set to appropriate operating levels prior to applying inputs on the i/os and controls for that port. 2. opt x selects the operating voltage levels for the i/os and controls on that port. if opt x is set to vih (3.3v), then that port's i/os and controls will operate at 3.3v levels and v ddqx must be supplied at 3.3v. if opt x is set to vil (0v), then that port's i/os and address controls will operate at 2.5v levels and v ddqx must be supplied at 2.5v. the opt pins are independent of one another?both ports can operate at 3.3v levels, both can operate at 2.5v levels, or either can operate at 3.3v with the other at 2.5v. 3. when repeat x is asserted, the counter will reset to the last valid address loaded via ads x . 4. accesses by the ports into specific banks are controlled by the bank address pins under the user's direct control: each port can access any bank of memory with the shared array that is not currently being accessed by the opposite port (i.e., ba 0l - ba 5l ba 0r - ba 5r ). in the event that both ports try to access the same bank at the same time, neither access will be valid, and data at the two specific addresses targeted by the ports within that bank may be corrupted (in the case that either or both ports are writing) or may result in invalid output (in the case that both ports are trying to read).
6.42 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges 5 notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ads , cnten , repeat are set as appropriate for address access. refer to truth table ii for details. 3. oe is an asynchronous input signal. 4. it is possible to read or write any combination of bytes during a given access. a few representative samples have been illust rated here. truth table i?read/write and enable control (1,2,3,4) oe 3 clk ce 0 ce 1 ub lb r/ w upper byte i/o 9-17 lower byte i/o 0-8 mode x h x x x x high-z high-z deselected?power down x x l x x x high-z high-z deselected?power down x l h h h x high-z high-z all bytes deselected x lhhll high-z d in write to lower byte only x lhlhl d in high-z write to upper byte only x lhlll d in d in write to both bytes l lhhlh high-z d out read lower byte only l lhlhh d out high-z read upper byte only l lhllh d out d out read both bytes h x x x x x x high-z high-z outputs disabled 5628 tbl 02 truth table ii?address and address counter control (1,2,7) notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. read and write operations are controlled by the appropriate setting of r/ w , ce 0 , ce 1 , ub / lb and oe . 3. outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ads and repeat are independent of all other memory control signals including ce 0 , ce 1 and ub / lb 5. the address counter advances if cnten = v il on the rising edge of clk, regardless of all other memory control signals including ce 0 , ce 1 , ub / lb . 6. when repeat is asserted, the counter will reset to the last valid address loaded via ads . this value is not set at power-up: a known location should be loaded via ads during initialization if desired. any subsequent ads access during operations will update the repeat address location. 7. the counter includes bank address and internal address. the counter will advance across bank boundaries. for example, if the counter is in bank 0, at address fffh, and is advanced one location, it will move to address 0h in bank 1. by the same token, the counter at fffh in bank 63 will advance to 0h in bank 0. refer to timing waveform of counter repeat, page 17. care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure ba 0l - ba 5l ba 0r - ba 5r ), as this condition will invalidate the access for both ports. please refer to the functional description on page 18 for details. address previous address addr used clk ads cnten repeat (6 ) i/o (3 ) mode an x an l (4) xhd i/o (n) external address used xanan + 1 h l (5) hd i/o (n+1) counter enabled?internal address generation x an + 1 an + 1 hh hd i/o (n+1) e xternal addre ss blocked?counter disab led (an + 1 reused) xxan xx l (4) d i/o (0) counter set to last valid ads load 5628 tbl 03
6.42 6 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges recommended operating temperature and supply voltage (1) recommended dc operating conditions with v ddq at 2.5v absolute maximum ratings (1) notes: 1. undershoot of v il > -1.5v for pulse width less than 10ns is allowed. 2. v term must not exceed v ddq + 100mv. 3. to select operation at 2.5v levels on the i/os and controls of a given port, the opt pin for that port must be set to v il (0v), and v ddqx for that port must be supplied as indicated above. notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v dd + 150mv for more than 25% of the cycle time or 4ns maximum, and is limited to < 20ma for the period of v term > v dd + 150mv. note: 1. this is the parameter t a . this is the "instant on" case temperature. grade ambient temperature gnd v dd commercial 0 o c to +70 o c0v3.3v + 150mv industrial -40 o c to +85 o c0v3.3v + 150mv 56 28 tb l 04 symbol parameter min. typ. max. unit v dd core supply voltage 3.15 3.3 3.45 v v ddq i/o supply voltage (3) 2.4 2.5 2.6 v v ss ground 0 0 0 v v ih input high voltage (address & control inputs) 1.7 ____ v ddq + 100mv (2) v v ih input high voltage - i/o (3 ) 1.7 ____ v ddq + 100mv (2) v v il input low voltage -0.3 (1 ) ____ 0.7 v 5628 tbl 05a symbol rating commercial & industrial unit v te rm (2 ) terminal voltage with respect to gnd -0.5 to +4.6 v t bias temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c i out dc output current 50 ma 5628 tbl 06 recommended dc operating conditions with v ddq at 3.3v notes: 1. undershoot of v il > -1.5v for pulse width less than 10ns is allowed. 2. v term must not exceed v ddq + 150mv. 3. to select operation at 3.3v levels on the i/os and controls of a given port, the opt pin for that port must be set to v ih (3.3v), and v ddqx for that port must be supplied as indicated above. symbol parameter min. typ. max. unit v dd core supply voltage 3.15 3.3 3.45 v v ddq i/o supply voltage (3) 3.15 3.3 3.45 v v ss ground 0 0 0 v v ih input high voltage (address & control inputs) (3 ) 2.0 ____ v ddq + 150mv (2) v v ih input high voltage - i/o (3 ) 2.0 ____ v ddq + 150mv (2) v v il input low voltage -0.3 (1 ) ____ 0.8 v 5628 tbl 05b
6.42 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges 7 dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v 150mv) notes: 1. at v dd < 2.0v leakages are undefined. 2. v ddq is selectable (3.3v/2.5v) via opt pins. refer to page 4 for details. symbol parameter test conditions 70v7339s unit min. max. |i li | input leakage current (1) v ddq = max., v in = 0v to v ddq ___ 10 a |i lo | output leakage current (1) ce 0 = v ih or ce 1 = v il , v out = 0v to v ddq ___ 10 a v ol (3.3v) output low voltage (2 ) i ol = +4ma, v ddq = min. ___ 0.4 v v oh (3.3v) output high voltage (2) i oh = -4ma, v ddq = min. 2.4 ___ v v ol (2.5v) output low voltage (2 ) i ol = +2ma, v ddq = min. ___ 0.4 v v oh (2.5v) output high voltage (2) i oh = -2ma, v ddq = min. 2.0 ___ v 5628 tbl 08 notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. 3. c out also references c i/o . capacitance (1) (t a = +25c, f = 1.0mh z ) pqfp only symbol parameter conditions (2 ) max. unit c in inp ut capacitance v in = 3dv 8 pf c out (3 ) output capacitance v out = 3dv 10.5 pf 5628 tbl 07
6.42 8 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges dc electrical characteristics over the operating temperature and supply voltage range (5) (v dd = 3.3v 150mv) notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using "ac test conditions" at input levels of gnd to 3v. 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. v dd = 3.3v, t a = 25c for typ, and are not production tested. i dd dc (f=0) = 120ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v ddq - 0.2v ce x > v ddq - 0.2v means ce 0x > v ddq - 0.2v or ce 1x < 0.2v "x" represents "l" for left port or "r" for right port. 70v7339s200 (7) com'l only 70v7339s166 (6) com'l & ind 70v7339s133 com'l & ind symbol parameter test condition version typ. (4) max. typ. (4) max. typ. (4) max. unit i dd dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled, f = f max (1) com'l s 815 950 675 790 550 645 ma ind s ____ ____ 675 830 550 675 i sb1 standby current (both ports - ttl level inputs) ce l = ce r = v ih f = f max (1) com'l s 340 410 275 340 250 295 ma ind s ____ ____ 275 355 250 310 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (3) active port outputs disabled, f=f max (1) com'l s 690 770 515 640 460 520 ma ind s ____ ____ 515 660 460 545 i sb3 full standby current (both ports - cmos level inputs) both ports ce l and ce r > v ddq - 0.2v, v in > v ddq - 0.2v or v in < 0.2v, f = 0 (2) com'l s 10 30 10 30 10 30 ma ind s ____ ____ 10 40 10 40 i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v ddq - 0.2v (5) v in > v ddq - 0.2v or v in < 0.2v, active port, outputs disabled, f = f max (1) com'l s 690 770 515 640 460 520 ma ind s ____ ____ 515 660 460 545 5628 tbl 09 6. 166mhz industrial temperature not available in bf-208 package. 7. this speed grade available when v ddq = 3.3.v for a specific port (i.e., optx = v ih ). this speed grade is available in bc-256 only.
6.42 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges 9 ac test conditions (v ddq - 3.3v/2.5v) figure 1. ac output test load. figure 2. output test load (for t cklz , t ckhz , t olz , and t ohz ). *including scope and jig. figure 3. typical output derating (lumped capacitive load). input pulse levels (address & controls) input pulse levels (i/os) input rise/fall times input timing reference levels output reference levels output load gnd to 3 . 0v/gnd to 2.4v gnd to 3.0v/gnd to 2.4v 2ns 1.5v/1.25v 1.5v/1.25v figures 1 and 2 5628 tbl 10 1.5v/1.25 50 ? 50 ? 5628 drw 03 10pf (tester) data out , 5628 drw 04 590 ? 5pf* 435 ? 3.3v data out , 833 ? 5pf* 770 ? 2.5v data out , -1 1 2 3 4 5 6 7 20.5 30 50 80 100 200 10.5pf is the i/o capacitance of this device, and 10pf is the ac test load capacitance. capacitance (pf) ? tcd (typical, ns) 5628 drw 05 ? ? ? ? ,
6.42 10 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges ac electrical characteristics over the operating temperature range (read and write cycle timing) (2,3) (v dd = 3.3v 150mv, t a = 0c to +70c) notes: 1. the pipelined output parameters (t cyc2 , t cd2 ) apply to either or both left and right ports when ft /pipe x = v ih . flow-through parameters (t cyc1 , t cd1 ) apply when ft /pipe x = v il for that port. 2. all input signals are synchronous with respect to the clock except for the asynchronous output enable ( oe ) and ft /pipe x . ft /pipe x should be treated as a dc signal, i.e. steady state during operation. 3. these values are valid for either level of v ddq (3.3v/2.5v). see page 4 for details on selecting the desired operating voltage levels for each port. 70v7339s200 (5) com'l only 70v7339s166 (3,4) com'l & ind 70v7339s133 (3) com'l & ind symbol parameter min.max.min.max.min.max.unit t cyc1 clock cycle time (flow-through) (1) 15 ____ 20 ____ 25 ____ ns t cyc2 clock cycle time (pipelined) (1) 5 ____ 6 ____ 7.5 ____ ns t ch1 clock high time (flow-through) (1) 5 ____ 6 ____ 7 ____ ns t cl1 clock low time (flow-through) (1) 5 ____ 6 ____ 7 ____ ns t ch2 clock high time (pipelined) (2) 2.0 ____ 2.1 ____ 2.6 ____ ns t cl2 clock low time (pipelined) (1) 2.0 ____ 2.1 ____ 2.6 ____ ns t r clock rise time ____ 1.5 ____ 1.5 ____ 1.5 ns t f clock fall time ____ 1.5 ____ 1.5 ____ 1.5 ns t sa address setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t ha address hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t sc chip enable setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t hc chip enable hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t sb byte enable setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t hb byte enable hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t sw r/w setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t hw r/w hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t sd input data setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t hd input data hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t sad ads setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t had ads hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t scn cnten setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t hcn cnten hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t srpt repeat setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t hrpt repeat hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t oe output enab le to data valid ____ 4.0 ____ 4.0 ____ 4.2 ns t olz output enab le to output low-z 0.5 ____ 0.5 ____ 0.5 ____ ns t ohz output enab le to output high-z 1 3.4 1 3.6 1 4.2 ns t cd1 clock to data valid (flow-through) (1) ____ 10 ____ 12 ____ 15 ns t cd2 clock to data valid (pipelined) (1) ____ 3.4 ____ 3.6 ____ 4.2 ns t dc data output hold after clock high 1 ____ 1 ____ 1 ____ ns t ckhz clock high to output high-z 1 3.4 1 3.6 1 4.2 ns t cklz clock high to output low-z 0.5 ____ 0.5 ____ 0.5 ____ ns port-to-port delay t co clock-to-clock offset 5.0 ____ 6.0 ____ 7.5 ____ ns 5628 tbl 11 4. 166mhz industrial temperature not available in bf-208 package. 5. this speed grade available when v ddq = 3.3.v for a specific port (i.e., optx = v ih ). this speed grade available in bc-256 package only.
6.42 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges 11 an an + 1 an + 2 an + 3 t cyc2 t ch2 t cl2 r/ w address ce 0 clk ce 1 ub / lb (3) data out oe t cd2 t cklz qn qn + 1 qn + 2 t ohz t olz t oe 5628 drw 06 (1) (1) t sc t hc t sb t hb t sw t hw t sa t ha t dc t sc t hc t sb t hb (4) (1 latency) (5) (5) timing waveform of read cycle for pipelined operation ( ads operation) ( ft /pipe 'x' = v ih ) (2) notes: 1. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 2. ads = v il , cnten and repeat = v ih . 3. the output is disabled (high-impedance state) by ce 0 = v ih , ce 1 = v il , ub / lb = v ih following the next rising edge of the clock. refer to truth table 1. 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. if ub / lb was high, then the appropriate byte of data out for qn + 2 would be disabled (high-impedance state). 6. "x" denotes left or right port. the diagram is with respect to that port. timing waveform of read cycle for flow-through output ( ft /pipe "x" = v il ) (2,6) an an + 1 an + 2 an + 3 t cyc1 t ch1 t cl1 r/ w address data out ce 0 clk oe t sc t hc t cd1 t cklz qn qn + 1 qn + 2 t ohz t olz t oe t ckhz 5628 drw 07 (5) (1) ce 1 be n (3) t sb t hb t sw t hw t sa t ha t dc t dc (4) t sc t hc t sb t hb (5)
6.42 12 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk q 0 q 1 q 3 data out(b1) t ch2 t cl2 t cyc2 address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) q 2 q 4 t cd2 t cd2 t ckhz t cd2 t cklz t dc t ckhz t cd2 t cklz t sc t hc t ckhz t cklz t cd2 a 6 a 6 t dc t sc t hc t sc t hc 5628 drw 08 timing waveform of a multi-device pipelined read (1,2) notes: 1. b1 represents device #1; b2 represents device #2. each device consists of one idt70v7339 for this waveform, and are setup for depth expansion in this example. address (b1) = address (b2) in this situation. 2. ub / lb , oe , and ads = v il ; ce 1(b1) , ce 1(b2) , r/ w , cnten , and repeat = v ih . timing waveform of a multi-device flow-through read (1,2) t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk 5628 drw 09 d 0 d 3 t cd1 t cklz t ckhz (1) (1) d 1 data out(b1) t ch1 t cl1 t cyc1 (1) address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) d 2 d 4 t cd1 t cd1 t ckhz t dc t cd1 t cklz t sc t hc (1) t ckhz (1) t cklz (1) t cd1 a 6 a 6 t dc t sc t hc t sc t hc d 5 t cd1 t cklz (1) t ckhz (1)
6.42 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges 13 clk "a" r/ w "a" bank address and address "a" data in"a" clk "b" r/ w "b" bank address and address "b" data out"b" t sw t hw t sa t ha t sd t hd t sw t hw t sa t ha t cd2 dn an an dn 5628 drw 10 t dc t co (3) timing waveform of port a write to pipelined port b read (1,2,4) timing waveform with port-to-port flow-through read (1,2,4) data in "a" clk "b" r/ w "b" bank address and address "a" r/ w "a" clk "a" bank address and address "b" an an dn t dc data out "b" 5628 drw 11 dn t sw t hw t sa t ha t sd t hd t hw t cd1 t co (3) t dc t sa t sw t ha notes: 1. ce 0 , be n, and ads = v il ; ce 1 , cnten , and repeat = v ih . 2. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 3. if t co < minimum specified, then operations from both ports are invalid. if t co minimum, then data from port "b" read is available on first port "b" clock cycle (i.e., time from write to valid read on opposite port will be t co + t cd1 ). 4. all timing is the same for both left and right ports. port "a" may be either left or right port. port "b" is the opposite of port "a". notes: 1. ce 0 , be n, and ads = v il ; ce 1 , cnten , and repeat = v ih . 2. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 3. if t co < minimum specified, then operations from both ports are invalid. if t co minimum, then data from port "b" read is available on first port "b" clock cycle (ie, time from write to valid read on opposite port will be t co + t cyc2 + t cd2 ). 4. all timing is the same for both left and right ports. port "a" may be either left or right port. port "b" is the opposite of port "a".
6.42 14 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 5628 drw 12 qn qn + 3 data out ce 1 ub / lb t cd2 t ckhz t cklz t cd2 t sc t hc t sb t hb t sw t hw t sa t ha t ch2 t cl2 t cyc2 read nop read t sd t hd (3) (1) t sw t hw write (4) timing waveform of pipelined read-to-write-to-read ( oe = v il ) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , be n , and ads = v il ; ce 1 , cnten , and repeat = v ih . "nop" is "no operation". 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 data in dn + 3 dn + 2 ce 0 clk 5628 drw 13 data out qn qn + 4 ce 1 ub / lb oe t ch2 t cl2 t cyc2 t cklz t cd2 t ohz t cd2 t sd t hd read write read t sc t hc t sb t hb t sw t hw t sa t ha (3) (1) t sw t hw (4) timing waveform of pipelined read-to-write-to-read ( oe controlled) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , ub / lb , and ads = v il ; ce 1 , cnten , and repeat = v ih . 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. this timing does not meet requirements for fastest speed grade. this waveform indicates how logically it could be done if tim ing so allows.
6.42 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges 15 timing waveform of flow-through read-to-write-to-read ( oe = v il ) (2) timing waveform of flow-through read-to-write-to-read ( oe controlled) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , ub / lb , and ads = v il ; ce 1 , cnten , and repeat = v ih . 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 5628 drw 14 qn data out ce 1 ub / lb t cd1 qn + 1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t cd1 t dc t ckhz qn + 3 t cd1 t dc t sc t hc t sb t hb t sw t hw t sa t ha read nop read t cklz (3) (1) t sw t hw write (4) r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 (3) data in dn + 2 ce 0 clk 5628 drw 15 qn data out ce 1 ub / lb t cd1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t dc qn + 4 t cd1 t dc t sc t hc t sb t hb t sw t hw t sa t ha read write read t cklz (1) dn + 3 t ohz t sw t hw oe t oe
6.42 16 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges address an clk data out qx - 1 (2) qx qn qn + 2 (2) qn + 3 ads cnten t cyc2 t ch2 t cl2 5628 drw 16 t sa t ha t sad t had t cd2 t dc read external address read with counter counter hold t sad t had t scn t hcn read with counter qn + 1 timing waveform of pipelined read with address counter advance (1) notes: 1. ce 0 , oe , ub / lb = v il ; ce 1 , r/ w , and repeat = v ih . 2. if there is no address change via ads = v il (loading a new address) or cnten = v il (advancing the address), i.e. ads = v ih and cnten = v ih , then the data output remains constant for subsequent clocks. timing waveform of flow-through read with address counter advance (1) address an clk data out qx (2) qn qn + 1 qn + 2 qn + 3 (2) qn + 4 ads cnten t cyc1 t ch1 t cl1 5628 drw 17 t sa t ha t sad t had read external address read with counter counter hold t cd1 t dc t sad t had t scn t hcn read with counter
6.42 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges 17 timing waveform of write with address counter advance (flow-through or pipelined inputs) (1,6) notes: 1. ce 0 , ub / lb , and r/ w = v il ; ce 1 and repeat = v ih . 2. ce 0 , ub / lb = v il ; ce 1 = v ih . 3. the "internal address" is equal to the "external address" when ads = v il and equals the counter output when ads = v ih . 4. no dead cycle exists during repeat operation. a read or write cycle may be coincidental with the counter repeat cycle: address loaded by last valid ads load will be accessed. for more information on repeat function refer to truth table ii. 5. cnten = v il advances internal address from ?an? to ?an +1?. the transition shown indicates the time required for the counter to advance. t he ?an +1?address is written to during this cycle. 6. the counter includes bank address and internal address. the counter will advance across bank boundaries. for example, if the counter is in bank 0, at address fffh, and is advanced one location, it will move to address 0h in bank 1. by the same token, the counter at fffh in bank 63 will advance to 0h in bank 0. 7. for pipelined mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations. address an clk data in dn dn + 1 dn + 1 dn + 2 ads cnten t ch2 t cl2 t cyc2 5628 drw 18 internal (3) address an (5) an + 1 an + 2 an + 3 an + 4 dn + 3 dn + 4 t sa t ha t sad t had write counter hold write with counter write external address write with counter t sd t hd t scn t hcn timing waveform of counter repeat for flow through mode (2,6,7) address an t cyc2 clk data in r/ w repeat 5628 drw 19 internal (3) address ads cnten write to ads address an advance counter write to an+1 advance counter write to an+2 hold counter write to an+2 repeat read last ads address an data out t sa t ha , an t sad t had t sw t hw t scn t hcn t srpt t hrpt t sd t hd t cd1 an+1 an+2 an+2 an an+1 an+2 an+2 d 0 d 1 d 2 d 3 an an+1 an+2 an+2 advance counter read an+1 advance counter read an+2 hold counter read an+2 (4)
6.42 18 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges functional description the idt70v7339 is a high-speed 512kx18 (9 mbit) synchronous bank-switchable dual-ported sram organized into 64 independent 8kx18 banks. based on a standard sram core instead of a traditional true dual-port memory core, this bank-switchable device offers the benefits of increased density and lower cost-per-bit while retaining many of the features of true dual-ports. these features include simultaneous, random access to the shared array, separate clocks per port, 166 mhz operating speed, full-boundary counters, and pinouts compatible with the idt70v3319 (256kx18) dual-port family. the two ports are permitted independent, simultaneous access into separate banks within the shared array. access by the ports into specific banks are controlled by the bank address pins under the user's direct control: each port can access any bank of memory with the shared array that is not currently being accessed by the opposite port (i.e., ba 0l - ba 5l ba 0r - ba 5r ). in the event that both ports try to access the same bank at the same time, neither access will be valid, and data at the two specific addresses targeted by the ports within that bank may be corrupted (in the case that either or both ports are writing) or may result in invalid output (in the case that both ports are trying to read). the idt70v7339 provides a true synchronous dual-port static ram interface. registered inputs provide minimal setup and hold times on address, data and all critical control inputs. an asynchronous output enable is provided to ease asynchronous bus interfacing. counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applica- tions. a high on ce 0 or a low on ce 1 for one clock cycle will power down the internal circuitry on each port (individually controlled) to reduce static power consumption. dual chip enables allow easier banking of multiple IDT70V7339S for depth expansion configurations. two cycles are re- quired with ce 0 low and ce 1 high to read valid data on the outputs. depth and width expansion the idt70v7339 features dual chip enables (refer to truth table i) in order to facilitate rapid and simple depth expansion with no requirements for external logic. figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. the idt70v7339 can also be used in applications requiring ex- panded width, as indicated in figure 4. through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 36-bits or wider. 5628 drw 20 idt70v7339 ce 0 ce 1 ce 1 ce 0 ce 0 ce 1 ba 6 (1) ce 1 ce 0 v dd v dd idt70v7339 idt70v7339 idt70v7339 control inputs control inputs control inputs control inputs be , r/ w , oe , clk, ads , repeat , cnten figure 4. depth and width expansion with idt70v7339 note: 1. in the case of depth expansion, the additional address pin logically serves as an extension of the bank address. accesses by th e ports into specific banks are controlled by the bank address pins under the user's direct control: each port can access any bank of memory within the shared array that is not curre ntly being accessed by the opposite port (i.e., ba 0l - ba 6l ba 0r - ba 6r ). in the event that both ports try to access the same bank at the same time, neither access will be valid, and data at the two specific addresses targeted by the parts within that bank may be corrupted (in the case that either or both parts are writing) or may result in invalid output (in the c ase that both ports are trying to read).
6.42 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges 19 jtag ac electrical characteristics (1,2,3,4) 70v7339 symbol parameter min. max. units t jcyc jtag clock input period 100 ____ ns t jch jtag clock high 40 ____ ns t jcl jtag clock low 40 ____ ns t jr jtag clock rise time ____ 3 (1) ns t jf jtag clock fall time ____ 3 (1) ns t jrst jtag reset 50 ____ ns t jrsr jtag reset recovery 50 ____ ns t jcd jtag data output ____ 25 ns t jdc jtag data output hold 0 ____ ns t js jtag setup 15 ____ ns t jh jtag hold 15 ____ ns 5628 tbl 12 notes: 1. guaranteed by design. 2. 30pf loading on external output signals. 3. refer to ac electrical test conditions stated earlier in this document. 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet. jtag timing specifications tck device inputs (1) / tdi/tms device outputs (2) / tdo trst t jcd t jdc t jrst t js t jh t jcyc t jrsr t jf t jcl t jr t jch 5628 drw 21 , figure 5. standard jtag timing notes: 1. device inputs = all device inputs except tdi, tms, trst, and tck. 2. device outputs = all device outputs except tdo.
6.42 20 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges identification register definitions instruction field value description revision number (31:28) 0x0 reserved for version number idt device id (27:12) 0x301 defines idt part number idt jedec id (11:1) 0x33 allows unique identification of device vendor as idt id register indicator bit (bit 0) 1 indicates the presence of an id register 5 628 tbl 13 scan register sizes register name bit size instruction (ir) 4 bypass (byr) 1 identification (idr) 32 boundary scan (bsr) note (3) 5628 tbl 14 system interface parameters instruction code description extest 0000 forces contents of the boundary scan cells onto the device outputs (1) . places the boundary scan register (bsr) between tdi and tdo. b ypass 1111 plac e s the b y p as s re g is te r (byr) b e twe e n tdi and tdo. idcode 0010 loads the id register (idr) with the vendor id code and places the register between tdi and tdo. highz 0100 places the bypass register (byr) between tdi and tdo. forces all device output drivers to a high-z state. clamp 0011 uses byr. forces contents of the boundary scan cells onto the device outputs. places the bypass register (byr) between tdi and tdo. sample/preload 0001 places the boundary scan register (bsr) between tdi and tdo. sample allows data from device inputs (2) and outputs (1 ) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the boundary scan cells via the tdi. reserved all other codes several combinations are reserved. do not use codes other than those identified above. 5 628 tbl 15 notes: 1. device outputs = all device outputs except tdo. 2. device inputs = all device inputs except tdi, tms, trst, and tck. 3. the boundary scan descriptive language (bsdl) file for this device is available on the idt website (www.idt.com), or by conta cting your local idt sales representative.
6.42 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges 21 ordering information datasheet document history 01/05/00: initial public offering 06/20/01: page 1 added jtag information for tqfp package page 4 & 22 changed tqfp package from da to dd corrected pin number on tqfp package from 100 to 110 page 20 increased t jcd from 20ns to 25ns 08/06/01: page 4 changed body size for dd package from 22mm x 22mm x1.6mm to 20mm x 20mm x 1.4mm page 9 changed i sb 3 values for commercial and industrial dc electrical characteristics 11/20/01: page 2, 3 & 4 added date revision for pin configurations page 11 changed t oe value in ac electrical characteristics, please refer to errata #smen-01-05 page 1 & 22 replaced tm logo with ? logo 03/18/02: page 1, 9, 11 & 22 added 200mhz specification page 9 tightened power numbers in dc electrical characteristics page 14 changed waveforms to show invalid operation if t co < minimum specified page 1 - 22 removed "preliminary" status 12/04/02: page 9, 11 & 22 designated 200mhz speed grade in bc-256 package only 01/16/04: page 11 added byte enable setup time and byte enable hold time parameters and values to all speed grades in the ac e lectrical characteristics table 07/25/08: page 9 corrected a typo in the dc chars table 01/29/09: page 22 removed "idt" from orderable part number notes: 1. available in bc-256 package only. 2. industrial temperature at 166mhz not available in the bf-208 package. 3. green parts available. for specific speeds, packages and powers contact your local sales office. 4. contact your local sales office for industrial temp range for other speeds, packages and powers. a power 999 speed a package a process/ temperature range blank i (4) commercial (0c to +70c) industrial (-40c to +85c) bf bc 208-pin fpbga 256-pin bga 200 166 133 xxxxx device type speed in megahertz 5628 drw 22 s standard power 70v7339 9mbit (512k x 18-bit) synchronous bank-switchable dual-port ram commercial only (1) commercial & industrial (2) commercial & industrial blank 8 tube of tray tape and reel a g (3) green a (bf208) (bc256)
6.42 22 IDT70V7339S high-speed 512k x 18 synchronous bank-switchable dual-port static ram industrial and commercial temperature ranges the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com ? datasheet document history (con't) 04/20/10: page 1 added green availability to features page 21 added green indicator to ordering information removed the dd 144-pin tqfp (dd-144) thin quad flatpack per pdn: f-08-01 08/11/15: page 2 & 3 removed the date from all of the pin configurations bf208 & bc256 page 21 added t&r indicator and updated footnotes for ordering information

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